As manufacturing of an integrated circuit becomes highly dense with numerous parasitic effects, it is increasingly difficult to determine a chip behavior from simulation. Build-in delay elements are used in a VLSI chip as a viable alternative for adjusting timing discrepancies. FIG. 1A schematically shows a typical circuit of a delay element according to the prior art. Transfer devices D1 101, D2 102, D3 103, D4 104 each have a controlled current path from the delay line 110 through a serially connected fixed value capacitor, C 105, 2C 106, 4C 107 or 8C 108, to ground respectively. In operation, when a transfer device is selectively turned on, current flows from the input line through the transfer device and then through the serially connected fixed value capacitor to ground. The resistive load (R.sub.L) present on the delay line in conjunction with the capacitance of the fixed capacitor form an RC circuit having a time constant (T) equal to T=R.sub.L *C. By turning on more than one transfer device, parallel capacitance is added thereby increasing the time constant.
The delay of the signal present on the delay line is increased as more parallel capacitance is added. This function is graphically shown in FIG. 1B where the rise time of the signal propagating through the delay line increases as capacitance is increased. A conventional solution does not allow for altering the delay in fix time intervals due to changing nature of a transistor's resistance. Accordingly, it is desirable to provide a programmable delay element that can provide a delay with many available delay combinations.